The present invention relates generally to the field of semiconductor structure and a method of forming the same, and more particularly to reducing the contact resistance of a back-end-of-the line (BEOL) interconnect structure primarily composed of graphene and metal.
Integrated circuit(s) typically include a plurality of semiconductor devices and interconnect wiring. Networks of metal interconnect wiring typically connect the semiconductor devices from a semiconductor portion of a semiconductor substrate. Multiple levels of metal interconnect wiring above the semiconductor portion of the semiconductor substrate are connected together to form a back-end-of-the line (BEOL) interconnect structure. Within such a structure, metal lines run parallel to the substrate and metal vias run perpendicular top the substrate.
Two developments in the last decade have contributed to increased performance of contemporary ICs. One such development is the use of copper as the interconnect metal of the BEOL interconnect structure. Copper is advantageous because it has a higher conductivity compared with other traditionally used interconnect metals such as, for example, aluminum. However, when compared to copper, other materials such as graphene have superior current carrying capacities and thermal conductivity, but many methods of producing graphene have presented numerous challenges which discouraged the inclusion of graphene in contemporary ICs.